Hardware emulation of stochastic p-bits for invertible logic

The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0's and 1's. A completely different paradigm is based on three-terminal stochastic units which could be called "p-bits", where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions

Weighted p-bits for FPGA implementation of probabilistic circuits

Probabilistic spin logic (PSL) is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve problems of optimization, inference and also to implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this paper we present a scalable FPGA implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped, and how invertibility can be applied to interesting problems such as the NP-complete Subset Sum Problem by solving a small instance of this problem in hardware

The Front Page for Probabilistic Spin Logic

While probabilistic neural networks are a staple of the neural network field, their study in the context of real hardware has been limited. Probabilistic spin logic entails the study of probabilistic neurons that have real hardware counterparts. This comes under a new effort, termed Purdue-P, whose goal it is to develop efficient, probabilistic neural network hardware to solve some of today’s most difficult problems. An important step in this effort has been the development of a website, purduep.com, to act as a “front page” for the effort. This website introduces the idea of probabilistic spin logic to newcomers, houses an online web simulator and blog, and provides instructions on how to access a powerful asynchronous p-computing co-processor through the cloud. The thoughts behind the flow of content, the web simulator, and cloud access of the coprocessor constitute the crux of the thesis

Hardware emulation of stochastic p-bits for invertible logic.

The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0's and 1's. A completely different paradigm is based on three-terminal stochastic units which could be called "p-bits", where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions

Weighted p -Bits for FPGA Implementation of Probabilistic Circuits.

Probabilistic spin logic is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits ( p -bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve the problems of optimization, inference, and implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this brief, we present a scalable field-programmable gate array implementation of such invertible p-circuits. We implement a "weighted" p -bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p -bits to which a large class of problems beyond invertible Boolean logic can be mapped and how invertibility can be applied to interesting problems such as the NP-complete subset sum problem by solving a small instance of this problem in hardware